Toshiba cache based on STT-MRAM 80% more economical than SRAM

Toshiba cache based on STT-MRAM 80% more economical than SRAM

Despite the fact that the conference ISSCC 2015 ended more last week, Toshiba has just now published a report on the development of a new scheme of STT-MRAM, which was presented during one of the reports.

It is alleged that the proposed technology for energy consumption up to 80% more economical than traditional SRAM-memory. At the same time, access is only 3.3 ns. STT-MRAM Toshiba is among the most energy efficient of all types of built-in memory.

In recent years, the market is developing rapidly SoC. Motor industry is a growing demand for chips for the Internet of Things, wearable electronics, smartphones, cloud data centers. In these applications, the capacity of SRAM-memory significantly increased, respectively, and increased energy efficiency requirements. One of the problems is the leakage currents SRAM which inevitably arise and lead to relatively large energy losses. A few days ago we mentioned the unique chip for Internet of Things with a capacity of only 400 leak PW. Toshiba, in turn, finds a promising solution to use as a cache-volatile memory, such as STT-MRAM. But the peripheral control circuits also consume relatively more power, so even with the problem of energy storage cost of the entire system cache as a whole remains relevant.

Toshiba cache based on STT-MRAM 80% more economical than SRAM

To solve this problem the company has developed a scheme with high-speed switching between active and off-state (transition duration is less than 100 ns). Further improvements have allowed further reduce power consumption during read and write data.

The ultimate goal of the project is the creation of such schemes, which will reduce the total power consumption of chips by 90%. Toshiba hopes to complete its development in the current fiscal year.

Toshiba cache based on STT-MRAM 80% more economical than SRAM updated: March 5, 2015 author: John Malkovich